The invention relates generally to electronic logic simulation, and deals more particularly with providing user-initiated set and hold inputs to logic simulation performed on parallel processors for different parts of one circuit.
Previously known logic simulators assist in the design, development and debugging of complex circuitry. For example, the logic simulator may determine if a proposed circuit design performs the requisite function and meets other specifications, before the circuitry is built. The simulator can simulate digital logic and even analog circuitry. Each logic simulator comprises one or more computer programs and data structures to simulate the circuitry. For each logic component, such as an AND gate, the logic simulator program includes a subroutine which performs a logical AND operation and maintains a data structure which stores the inputs and resultant outputs. The computer program can also supply some or all of the digital input signals to the simulated circuit, to initiate operation of the simulated circuit. The digital input signals simulate electronic signals that would be supplied by other circuitry or programming associated with the simulated circuit.
There are different types of logic simulators. Cycle simulators evaluate all gates at each simulation time, and record the respective outputs and states. Because all gates are evaluated at each simulation time, cycle simulators are easy to design, but slow to execute and require much memory.
Event simulators evaluate only those gates whose input(s) have changed at evaluation time. This technique requires sophisticated routines to determine which gates have changed inputs at evaluation time, but requires fewer evaluations at each simulation time compared to cycle simulators. In order to improve the speed of event simulators, different parts of one complex circuit can be simulated on multiple processors or nodes. One part of the circuit simulated on one node can interact with, i.e. provide input signals for and receive output signals from, another part of the same circuit simulated on another node by sending output messages and receiving input messages, respectively.
There are known techniques for coordinating execution of different portions of one simulated logic circuit whose portions are distributed on multiple nodes.
In a "synchronous" technique, all portions of the logic simulation are controlled by a common clock and performed synchronously with all other portions. While this technique provides accurate simulation, no portion of the logic simulation can advance its operation faster than the common clock and many portions have no activity during many of the clock cycles. In a "conservative" technique, each node uses its own simulation clock and proceeds at its own pace (advancing its own clock) until the node requires an input from another (neighbor) node. Then, the node waits for the input. In this technique, each node may spend much time waiting for inputs from other nodes. In a "virtual time" technique, each node uses its own simulation clock and proceeds at its own pace. However, unlike the conservative technique, if one node requires an input from another node and this other node has not yet reached the point of providing the input, then the one node predicts the input and continues on. Later, this other node will provide the input, and if the prediction was wrong, then the one node and any other nodes which received inputs from the one node must be rolled-back and re-executed to reflect the correct input. In most virtual time logic simulators, the predictions are a repetition of the previous input and this is usually correct because in a typical circuit, most inputs do not change often. Thus, the virtual time technique may substantially increase the overall speed of operation of the logic simulation.
In the previously known virtual time technique, when a node detects exhaustion of its resources, it will request a global virtual time calculation. A message is sent to all other nodes and all nodes respond to the requestor with their respective simulation times. After receiving the responses from all the nodes, the requestor determines the minimum of the simulation times. This minimum represents a global virtual time (GVT) for the entire system. All gate outputs and states at or before the GVT are valid because none of the nodes will provide an input for another node at an earlier time and therefore, none of the nodes will be rolled-back before the GVT. It was also known in the virtual time technique for each of the nodes to report to the host a minimum virtual time instead of the actual simulation time. The minimum virtual time is the minimum of the actual simulation time and the virtual time of any messages that the node has sent to another node and not yet received an acknowledgment. This ensures that the resultant GVT cannot be undermined by any messages in transit. After all nodes complete their portion of the logic simulation, a host user may request various nets and states of the simulated logic.
An exemplary virtual time system comprising a plurality of processor nodes with means for calculating GVT at any of the processor nodes is described in U.S. Pat. No. 5,250,943, commonly assigned herewith and incorporated herein by reference.
During logic simulation in a virtual time logic simulator, a user may desire to set (or hold) elements of the simulated logic at specific values for a period of simulation time. However, the known virtual time logic simulation systems do not support user modification of the inputs to, or the states of, simulated logic circuit elements during simulation. A general object of the present invention is, therefore, to enable a user to introduce sets or holds for identified elements of a simulated logic circuit during simulation.